// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vasic_wrapper.h for the primary calling header

#ifndef VERILATED_VASIC_WRAPPER___024ROOT_H_
#define VERILATED_VASIC_WRAPPER___024ROOT_H_  // guard

#include "verilated.h"
class Vasic_wrapper_GIN_Bus__T4;
class Vasic_wrapper_GON_Bus__T4;
class Vasic_wrapper_PE;


class Vasic_wrapper__Syms;

class alignas(VL_CACHE_LINE_BYTES) Vasic_wrapper___024root final : public VerilatedModule {
  public:
    // CELLS
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__0__KET____DOT__PE_COL__BRA__0__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__0__KET____DOT__PE_COL__BRA__1__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__0__KET____DOT__PE_COL__BRA__2__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__0__KET____DOT__PE_COL__BRA__3__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__0__KET____DOT__PE_COL__BRA__4__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__0__KET____DOT__PE_COL__BRA__5__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__0__KET____DOT__PE_COL__BRA__6__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__0__KET____DOT__PE_COL__BRA__7__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__1__KET____DOT__PE_COL__BRA__0__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__1__KET____DOT__PE_COL__BRA__1__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__1__KET____DOT__PE_COL__BRA__2__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__1__KET____DOT__PE_COL__BRA__3__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__1__KET____DOT__PE_COL__BRA__4__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__1__KET____DOT__PE_COL__BRA__5__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__1__KET____DOT__PE_COL__BRA__6__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__1__KET____DOT__PE_COL__BRA__7__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__2__KET____DOT__PE_COL__BRA__0__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__2__KET____DOT__PE_COL__BRA__1__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__2__KET____DOT__PE_COL__BRA__2__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__2__KET____DOT__PE_COL__BRA__3__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__2__KET____DOT__PE_COL__BRA__4__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__2__KET____DOT__PE_COL__BRA__5__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__2__KET____DOT__PE_COL__BRA__6__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__2__KET____DOT__PE_COL__BRA__7__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__3__KET____DOT__PE_COL__BRA__0__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__3__KET____DOT__PE_COL__BRA__1__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__3__KET____DOT__PE_COL__BRA__2__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__3__KET____DOT__PE_COL__BRA__3__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__3__KET____DOT__PE_COL__BRA__4__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__3__KET____DOT__PE_COL__BRA__5__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__3__KET____DOT__PE_COL__BRA__6__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__3__KET____DOT__PE_COL__BRA__7__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__4__KET____DOT__PE_COL__BRA__0__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__4__KET____DOT__PE_COL__BRA__1__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__4__KET____DOT__PE_COL__BRA__2__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__4__KET____DOT__PE_COL__BRA__3__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__4__KET____DOT__PE_COL__BRA__4__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__4__KET____DOT__PE_COL__BRA__5__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__4__KET____DOT__PE_COL__BRA__6__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__4__KET____DOT__PE_COL__BRA__7__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__5__KET____DOT__PE_COL__BRA__0__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__5__KET____DOT__PE_COL__BRA__1__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__5__KET____DOT__PE_COL__BRA__2__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__5__KET____DOT__PE_COL__BRA__3__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__5__KET____DOT__PE_COL__BRA__4__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__5__KET____DOT__PE_COL__BRA__5__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__5__KET____DOT__PE_COL__BRA__6__KET____DOT__PE;
    Vasic_wrapper_PE* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ROW__BRA__5__KET____DOT__PE_COL__BRA__7__KET____DOT__PE;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__GIN_XBUS__BRA__0__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__GIN_XBUS__BRA__1__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__GIN_XBUS__BRA__2__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__GIN_XBUS__BRA__3__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__GIN_XBUS__BRA__4__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__GIN_XBUS__BRA__5__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__GIN_XBUS__BRA__0__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__GIN_XBUS__BRA__1__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__GIN_XBUS__BRA__2__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__GIN_XBUS__BRA__3__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__GIN_XBUS__BRA__4__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__GIN_XBUS__BRA__5__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__GIN_XBUS__BRA__0__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__GIN_XBUS__BRA__1__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__GIN_XBUS__BRA__2__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__GIN_XBUS__BRA__3__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__GIN_XBUS__BRA__4__KET____DOT__XBus;
    Vasic_wrapper_GIN_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__GIN_XBUS__BRA__5__KET____DOT__XBus;
    Vasic_wrapper_GON_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__0__KET____DOT__XBus;
    Vasic_wrapper_GON_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__1__KET____DOT__XBus;
    Vasic_wrapper_GON_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__2__KET____DOT__XBus;
    Vasic_wrapper_GON_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__3__KET____DOT__XBus;
    Vasic_wrapper_GON_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__4__KET____DOT__XBus;
    Vasic_wrapper_GON_Bus__T4* __PVT__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__5__KET____DOT__XBus;

    // DESIGN SPECIFIC STATE
    // Anonymous structures to workaround compiler member-count bugs
    struct {
        VL_IN8(ACLK,0,0);
        VL_IN8(ARESETn,0,0);
        VL_OUT8(ASIC_interrupt,0,0);
        VL_IN8(AWID_S,7,0);
        VL_IN8(AWLEN_S,7,0);
        VL_IN8(AWSIZE_S,2,0);
        VL_IN8(AWBURST_S,1,0);
        VL_IN8(AWVALID_S,0,0);
        VL_OUT8(AWREADY_S,0,0);
        VL_IN8(WSTRB_S,3,0);
        VL_IN8(WLAST_S,0,0);
        VL_IN8(WVALID_S,0,0);
        VL_OUT8(WREADY_S,0,0);
        VL_OUT8(BID_S,7,0);
        VL_OUT8(BRESP_S,1,0);
        VL_OUT8(BVALID_S,0,0);
        VL_IN8(BREADY_S,0,0);
        VL_IN8(ARID_S,7,0);
        VL_IN8(ARLEN_S,7,0);
        VL_IN8(ARSIZE_S,2,0);
        VL_IN8(ARBURST_S,1,0);
        VL_IN8(ARVALID_S,0,0);
        VL_OUT8(ARREADY_S,0,0);
        VL_OUT8(RID_S,7,0);
        VL_OUT8(RRESP_S,1,0);
        VL_OUT8(RLAST_S,0,0);
        VL_OUT8(RVALID_S,0,0);
        VL_IN8(RREADY_S,0,0);
        VL_OUT8(AWID_M,3,0);
        VL_OUT8(AWLEN_M,7,0);
        VL_OUT8(AWSIZE_M,2,0);
        VL_OUT8(AWBURST_M,1,0);
        VL_OUT8(AWVALID_M,0,0);
        VL_IN8(AWREADY_M,0,0);
        VL_OUT8(WSTRB_M,3,0);
        VL_OUT8(WLAST_M,0,0);
        VL_OUT8(WVALID_M,0,0);
        VL_IN8(WREADY_M,0,0);
        VL_IN8(BID_M,3,0);
        VL_IN8(BRESP_M,1,0);
        VL_IN8(BVALID_M,0,0);
        VL_OUT8(BREADY_M,0,0);
        VL_OUT8(ARID_M,3,0);
        VL_OUT8(ARLEN_M,7,0);
        VL_OUT8(ARSIZE_M,2,0);
        VL_OUT8(ARBURST_M,1,0);
        VL_OUT8(ARVALID_M,0,0);
        VL_IN8(ARREADY_M,0,0);
        VL_IN8(RID_M,3,0);
        VL_IN8(RRESP_M,1,0);
        VL_IN8(RLAST_M,0,0);
        VL_IN8(RVALID_M,0,0);
        VL_OUT8(RREADY_M,0,0);
        CData/*0:0*/ asic_wrapper__DOT__GLB_EN;
        CData/*0:0*/ asic_wrapper__DOT__GLB_EN_dma;
        CData/*0:0*/ asic_wrapper__DOT__GLB_WEB;
        CData/*0:0*/ asic_wrapper__DOT__GLB_WEB_dma;
        CData/*0:0*/ asic_wrapper__DOT__GLB_MODE;
        CData/*0:0*/ asic_wrapper__DOT__GLB_MODE_dma;
        CData/*0:0*/ asic_wrapper__DOT__glb_mux;
        CData/*1:0*/ asic_wrapper__DOT__DMA_MODE;
        CData/*2:0*/ asic_wrapper__DOT__cs_slave;
        CData/*2:0*/ asic_wrapper__DOT__cs_slave_next;
        CData/*7:0*/ asic_wrapper__DOT__BID_S_next;
    };
    struct {
        CData/*7:0*/ asic_wrapper__DOT__RID_S_next;
        CData/*0:0*/ asic_wrapper__DOT__write_error;
        CData/*0:0*/ asic_wrapper__DOT__write_error_next;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__DMAEN;
        CData/*1:0*/ asic_wrapper__DOT__DMA_0__DOT__DMABYTE_BIAS;
        CData/*1:0*/ asic_wrapper__DOT__DMA_0__DOT__DMAMODE;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__DMADIR;
        CData/*7:0*/ asic_wrapper__DOT__DMA_0__DOT__burst_len;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__AXI_enable;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__GLB_enable;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT____Vcellinp__DMA_controller_0__AXI_done;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__FIFO_push_i_R;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__FIFO_pop_i_G;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__FIFO_push_i_G;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__FIFO_pop_i_W;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__FIFO_full;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT__FIFO_empty;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT____Vcellinp__DMA_FIFO_0__pop_i;
        CData/*0:0*/ asic_wrapper__DOT__DMA_0__DOT____Vcellinp__DMA_FIFO_0__push_i;
        CData/*2:0*/ asic_wrapper__DOT__DMA_0__DOT__cs_master_R;
        CData/*2:0*/ asic_wrapper__DOT__DMA_0__DOT__cs_master_R_next;
        CData/*2:0*/ asic_wrapper__DOT__DMA_0__DOT__cs_master_W;
        CData/*2:0*/ asic_wrapper__DOT__DMA_0__DOT__cs_master_W_next;
        CData/*2:0*/ asic_wrapper__DOT__DMA_0__DOT__cs_glb;
        CData/*2:0*/ asic_wrapper__DOT__DMA_0__DOT__cs_glb_next;
        CData/*7:0*/ asic_wrapper__DOT__DMA_0__DOT__burst_count;
        CData/*7:0*/ asic_wrapper__DOT__DMA_0__DOT__burst_count_next;
        CData/*1:0*/ asic_wrapper__DOT__DMA_0__DOT__GLB_A_bias;
        CData/*1:0*/ asic_wrapper__DOT__DMA_0__DOT__GLB_A_bias_next;
        CData/*1:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_controller_0__DOT__DMA_state;
        CData/*1:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_controller_0__DOT__DMA_state_next;
        CData/*7:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_controller_0__DOT__burst_len_next;
        CData/*5:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_FIFO_0__DOT__write_ptr;
        CData/*5:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_FIFO_0__DOT__read_ptr;
        CData/*6:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_FIFO_0__DOT__fifo_count;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__ifmap_XID_scan_in;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__filter_XID_scan_in;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__ipsum_XID_scan_in;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__opsum_XID_scan_in;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__set_YID;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__ifmap_YID_scan_in;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__ipsum_YID_scan_in;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__opsum_YID_scan_in;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PEA_ifmap_ready;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__ifmap_tag_X;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PEA_filter_ready;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__filter_tag_X;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__filter_tag_Y;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PEA_ipsum_ready;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__ipsum_tag_X;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__ipsum_tag_Y;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__opsum_tag_X;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__opsum_tag_Y;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__ppu_data_out;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__relu_sel;
        CData/*4:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__LN_config;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__XBus_valid;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT____Vcellinp__GIN_XBUS__BRA__0__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT____Vcellinp__GIN_XBUS__BRA__1__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT____Vcellinp__GIN_XBUS__BRA__2__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT____Vcellinp__GIN_XBUS__BRA__3__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT____Vcellinp__GIN_XBUS__BRA__4__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT____Vcellinp__GIN_XBUS__BRA__5__KET____DOT__XBus__slave_ready;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT__valid_mask;
    };
    struct {
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT__mc_valid;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT__mc_ready;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__0__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__1__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__2__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__3__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__4__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__5__KET____DOT__MC__id;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__XBus_valid;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT____Vcellinp__GIN_XBUS__BRA__0__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT____Vcellinp__GIN_XBUS__BRA__1__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT____Vcellinp__GIN_XBUS__BRA__2__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT____Vcellinp__GIN_XBUS__BRA__3__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT____Vcellinp__GIN_XBUS__BRA__4__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT____Vcellinp__GIN_XBUS__BRA__5__KET____DOT__XBus__slave_ready;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT__valid_mask;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT__mc_valid;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT__mc_ready;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__0__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__1__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__2__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__3__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__4__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__5__KET____DOT__MC__id;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__XBus_valid;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT____Vcellinp__GIN_XBUS__BRA__0__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT____Vcellinp__GIN_XBUS__BRA__1__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT____Vcellinp__GIN_XBUS__BRA__2__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT____Vcellinp__GIN_XBUS__BRA__3__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT____Vcellinp__GIN_XBUS__BRA__4__KET____DOT__XBus__slave_ready;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT____Vcellinp__GIN_XBUS__BRA__5__KET____DOT__XBus__slave_ready;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT__valid_mask;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT__mc_valid;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT__mc_ready;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__0__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__1__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__2__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__3__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__4__KET____DOT__MC__id;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT____Vcellout__GIN_MC__BRA__5__KET____DOT__MC__id;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__mc_valid;
        CData/*6:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__select_valid;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__0__KET____DOT__MC_i__ready_out;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__0__KET____DOT__MC_i__id;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__1__KET____DOT__MC_i__ready_out;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__1__KET____DOT__MC_i__id;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__2__KET____DOT__MC_i__ready_out;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__2__KET____DOT__MC_i__id;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__3__KET____DOT__MC_i__ready_out;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__3__KET____DOT__MC_i__id;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__4__KET____DOT__MC_i__ready_out;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__4__KET____DOT__MC_i__id;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__5__KET____DOT__MC_i__ready_out;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT____Vcellout__GON_MC__BRA__5__KET____DOT__MC_i__id;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__GON_MC__BRA__0__KET____DOT__MC_i__DOT____VdfgRegularize_h4d08139e_0_0;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__GON_MC__BRA__1__KET____DOT__MC_i__DOT____VdfgRegularize_h4d08139e_0_0;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__GON_MC__BRA__2__KET____DOT__MC_i__DOT____VdfgRegularize_h4d08139e_0_0;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__GON_MC__BRA__3__KET____DOT__MC_i__DOT____VdfgRegularize_h4d08139e_0_0;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__GON_MC__BRA__4__KET____DOT__MC_i__DOT____VdfgRegularize_h4d08139e_0_0;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__GON_MC__BRA__5__KET____DOT__MC_i__DOT____VdfgRegularize_h4d08139e_0_0;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__pq_data_out;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__pq_data_out_reg;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__relu_data_in;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__post_quant_0__DOT__overflow_pos;
    };
    struct {
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__post_quant_0__DOT__overflow_neg;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__Comparator_Qint8_0__DOT__data_max;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__Comparator_Qint8_0__DOT__data_max_next;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__Comparator_Qint8_0__DOT__bigger;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__ReLU_Qint8_0__DOT__relu_out;
        CData/*4:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__cs;
        CData/*4:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__ns;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_x;
        CData/*1:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_y1;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_y2;
        CData/*1:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_c;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_filt;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_PP_filt;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_W;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__PPU_count_F;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_h;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_H;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_E;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_e;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_PPU;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_PP_filt_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_h_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_e_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_F_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_C_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_PPU_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_m_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_E_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_M_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_H_reset;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_c_reset;
        CData/*3:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__valid_e;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_str_m;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_str_f;
        CData/*2:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_str_e;
        CData/*5:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__PP_filt;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT____VdfgRegularize_hfb48745a_0_2;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT____VdfgRegularize_hfb48745a_0_10;
        CData/*0:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT____VdfgRegularize_hfb48745a_0_14;
        CData/*7:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT____VdfgRegularize_hfb48745a_0_15;
        CData/*0:0*/ __VstlDidInit;
        CData/*0:0*/ __VstlFirstIteration;
        CData/*0:0*/ __VicoFirstIteration;
        CData/*0:0*/ __Vtrigprevexpr___TOP__ACLK__0;
        CData/*0:0*/ __VactDidInit;
        CData/*0:0*/ __VactContinue;
        SData/*15:0*/ asic_wrapper__DOT__GLB_A;
        SData/*15:0*/ asic_wrapper__DOT__GLB_A_asic;
        SData/*15:0*/ asic_wrapper__DOT__DMA_0__DOT__DMAGLB_ADDR;
        SData/*15:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_WORD_LEN;
        SData/*15:0*/ asic_wrapper__DOT__DMA_0__DOT____Vcellout__DMA_controller_0__glb_addr;
        SData/*13:0*/ asic_wrapper__DOT__DMA_0__DOT__GLB_A_word;
        SData/*13:0*/ asic_wrapper__DOT__DMA_0__DOT__GLB_A_word_next;
        SData/*13:0*/ asic_wrapper__DOT__DMA_0__DOT__counter_R;
        SData/*13:0*/ asic_wrapper__DOT__DMA_0__DOT__counter_W;
        SData/*13:0*/ asic_wrapper__DOT__DMA_0__DOT__counter_R_next;
        SData/*13:0*/ asic_wrapper__DOT__DMA_0__DOT__counter_W_next;
        SData/*15:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_controller_0__DOT__glb_addr_next;
        SData/*10:0*/ asic_wrapper__DOT__asic_0__DOT__PE_config;
        SData/*9:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_m;
        SData/*9:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_C;
        SData/*9:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__count_M;
        SData/*11:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__eF;
        SData/*15:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__EF;
    };
    struct {
        SData/*13:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__C9;
        SData/*9:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT____VdfgRegularize_hfb48745a_0_9;
        VL_IN(AWADDR_S,31,0);
        VL_IN(WDATA_S,31,0);
        VL_IN(ARADDR_S,31,0);
        VL_OUT(RDATA_S,31,0);
        VL_OUT(AWADDR_M,31,0);
        VL_OUT(WDATA_M,31,0);
        VL_OUT(ARADDR_M,31,0);
        VL_IN(RDATA_M,31,0);
        IData/*31:0*/ asic_wrapper__DOT__GLB_DI;
        IData/*31:0*/ asic_wrapper__DOT__GLB_DO;
        IData/*31:0*/ asic_wrapper__DOT__GLB_DO_asic;
        IData/*31:0*/ asic_wrapper__DOT__addr_S_reg;
        IData/*31:0*/ asic_wrapper__DOT__addr_S_reg_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_ENABLE;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_ENABLE_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_MAPPING_PARAM;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_MAPPING_PARAM_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_SHAPE_PARAM1;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_SHAPE_PARAM1_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_SHAPE_PARAM2;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_SHAPE_PARAM2_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_IFMAP_ADDR;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_IFMAP_ADDR_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_FILTER_ADDR;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_FILTER_ADDR_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_BIAS_ADDR;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_BIAS_ADDR_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_OPSUM_ADDR;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_OPSUM_ADDR_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_GLB_FILTER_ADDR;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_GLB_FILTER_ADDR_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_GLB_OFMAP_ADDR;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_GLB_OFMAP_ADDR_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_GLB_BIAS_ADDR;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_GLB_BIAS_ADDR_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_IFMAP_LEN;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_IFMAP_LEN_next;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_OFMAP_LEN;
        IData/*31:0*/ asic_wrapper__DOT__ASIC_OFMAP_LEN_next;
        IData/*31:0*/ asic_wrapper__DOT__GLB_0__DOT__BWEB;
        IData/*31:0*/ asic_wrapper__DOT__GLB_0__DOT__SRAM_DI;
        IData/*31:0*/ asic_wrapper__DOT__GLB_0__DOT__i_SRAM__DOT__latched_DO;
        IData/*31:0*/ asic_wrapper__DOT__DMA_0__DOT__DMADRAM_ADDR;
        IData/*31:0*/ asic_wrapper__DOT__DMA_0__DOT__dram_addr;
        IData/*31:0*/ asic_wrapper__DOT__DMA_0__DOT__glb_addr;
        IData/*31:0*/ asic_wrapper__DOT__DMA_0__DOT__FIFO_data_o;
        IData/*31:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_controller_0__DOT__word_len_reg;
        IData/*31:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_controller_0__DOT__dram_addr_next;
        IData/*31:0*/ asic_wrapper__DOT__DMA_0__DOT__DMA_controller_0__DOT__word_len_reg_next;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__GLB_data_in_PEarray;
        VlWide<48>/*1535:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON_opsum;
        VlWide<48>/*1535:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__LN_ipsum;
        VlWide<48>/*1535:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ipsum;
        VlWide<48>/*1535:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_opsum;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT__j;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT__j;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT__j;
        VlWide<6>/*191:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__XBus_data;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__PPU__DOT__post_quant_0__DOT__data_shifted;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__mul1_src1;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__mul1_src2;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__mul1_res;
    };
    struct {
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__mul2_src1;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__mul2_src2;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__mul2_res;
        IData/*31:0*/ asic_wrapper__DOT__asic_0__DOT__asic_controller_0__DOT__mul3_res;
        IData/*31:0*/ __VactIterCount;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_en;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_filter_ready;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_ipsum_valid;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON_opsum_valid;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON_opsum_ready;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__LN_ipsum_valid;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__LN_ipsum_ready;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ipsum_valid;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_ipsum_ready;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_opsum_valid;
        QData/*47:0*/ asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__PE_opsum_ready;
        VlUnpacked<VlUnpacked<IData/*31:0*/, 32>, 512> asic_wrapper__DOT__GLB_0__DOT__i_SRAM__DOT__MEMORY;
        VlUnpacked<IData/*31:0*/, 64> asic_wrapper__DOT__DMA_0__DOT__DMA_FIFO_0__DOT__fifo_mem;
        VlUnpacked<CData/*3:0*/, 7> asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__scan_chain;
        VlUnpacked<CData/*2:0*/, 7> asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IFMAP__DOT__YBus__DOT__ID_scan_chain;
        VlUnpacked<CData/*3:0*/, 7> asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__scan_chain;
        VlUnpacked<CData/*2:0*/, 7> asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_FILTER__DOT__YBus__DOT__ID_scan_chain;
        VlUnpacked<CData/*3:0*/, 7> asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__scan_chain;
        VlUnpacked<CData/*2:0*/, 7> asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GIN_IPSUM__DOT__YBus__DOT__ID_scan_chain;
        VlUnpacked<CData/*3:0*/, 7> asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__XID_scan_chain;
        VlUnpacked<IData/*31:0*/, 7> asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__select_data;
        VlUnpacked<CData/*2:0*/, 7> asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__ID_scan_chain;
        VlUnpacked<IData/*31:0*/, 7> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__select_data__0;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__5__KET____DOT__XBus____PVT__select_data__0;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__4__KET____DOT__XBus____PVT__select_data__0;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__3__KET____DOT__XBus____PVT__select_data__0;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__2__KET____DOT__XBus____PVT__select_data__0;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__1__KET____DOT__XBus____PVT__select_data__0;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__0__KET____DOT__XBus____PVT__select_data__0;
        VlUnpacked<IData/*31:0*/, 7> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__Y_Bus__DOT__select_data__1;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__5__KET____DOT__XBus____PVT__select_data__1;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__4__KET____DOT__XBus____PVT__select_data__1;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__3__KET____DOT__XBus____PVT__select_data__1;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__2__KET____DOT__XBus____PVT__select_data__1;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__1__KET____DOT__XBus____PVT__select_data__1;
        VlUnpacked<IData/*31:0*/, 9> __Vtrigprevexpr___TOP__asic_wrapper__DOT__asic_0__DOT__PE_array__DOT__GON__DOT__GON_XBUS__BRA__0__KET____DOT__XBus____PVT__select_data__1;
        VlUnpacked<CData/*0:0*/, 19> __Vm_traceActivity;
    };
    VlTriggerVec<8> __VstlTriggered;
    VlTriggerVec<1> __VicoTriggered;
    VlTriggerVec<8> __VactTriggered;
    VlTriggerVec<8> __VnbaTriggered;

    // INTERNAL VARIABLES
    Vasic_wrapper__Syms* const vlSymsp;

    // CONSTRUCTORS
    Vasic_wrapper___024root(Vasic_wrapper__Syms* symsp, const char* v__name);
    ~Vasic_wrapper___024root();
    VL_UNCOPYABLE(Vasic_wrapper___024root);

    // INTERNAL METHODS
    void __Vconfigure(bool first);
};


#endif  // guard
